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4 mhz, 7 nv/hz, low offset and drift, high precision amplifier data sheet ada4077 - 2 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibi lity is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features low offset voltage (maximum specifications) b - grade: 25 v (soic) a - grade: 50 v (soic), 90 v (msop) very low offset voltage drift b - grade: 0.25 v/c (soic) a - grade: 0.5 5 v/c (soic) and 1.2 v/c (msop) , specified ove r ?40c to +125c, msl1 rated low input bias current: 1 .0 na maximum low noise: 7 nv/hz typical cmrr, psrr, and a vo > 120 db minimum low supply current : 40 0 a per amplifier typical wide b andwidth: 4.0 mhz d ual - sup ply operation: 5 v to 1 5 v unity - gain stable no phase reversal applications process control front - end amplifiers wireless base station control circuits optical network control circuits instrumentation sensors and controls : t hermocouples , r esistor thermal detectors (rtds) , s train bridges , and s hunt current measurements precision filters general description the ada4077 - 2 is a dual amplifier featuring extremely low offset voltage and drift and low input bias current, noise, and power consump t ion . outputs are stable with capacitive loads of more than 1000 pf with no external compensati on. applications for th is amplifier include sensor signal conditioning ( such as thermocouples, rtds, strain gauges), proce ss control front - end amplifiers, and precision diode power measurement in optical and wireless transmission systems. the ada4077 - 2 is useful in line powered and portable instrumentation , precision filters , and voltage or curren t measurement and level setting . unlike the amplifiers of some competitors , t he ada4077 - 2 is specified over the extended industrial temperature range for operation from ?40c to +125c with msl1 rating for the most demanding operating environments. it is available in 8 - lead soic (including the b - g rade) and msop (a - g rade only) packages. pin connection diagrams figure 1 . ada4077 - 2 pin configuration, 8 - lead msop figure 2 . ada4077 - 2 pin configuration, 8 - lead soic_n figure 3 . offset voltage distribution table 1. evolution of p recision devices by generation out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t o p view (not to scale) 10238-001 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t o p view (not to scale) 10238-002 v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-103 v sy = 5v soic op amp 1st 2nd 3rd 4th 5th 6th single op07 op77 op177 op1177 ad8677 dual op2177 ada4077 - 2 quad op4177
ada4077 - 2 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 pin connection diagrams ............................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics, 5.0 v ............................................... 3 electrical characteristics, 15.0 v ............................................. 4 absolute maximum ratings ....................................................... 5 thermal resistance ...................................................................... 5 pin configurations and function descriptions ............................6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 16 applications information .............................................................. 17 output phase reversal ............................................................... 17 low power linearized rtd ...................................................... 17 prop er board layout .................................................................. 18 packaging and ordering information ......................................... 19 outline dimensions ................................................................... 19 ordering g uide .......................................................................... 20 revision history 10/ 12 revision 0: initial version
data sheet ada4077 - 2 rev. 0 | page 3 of 20 specifications electrical character istics , 5.0 v v s y = 5.0 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 2. parameter symbol test conditions/comme nt s min typ max unit input characteristics offset voltage (b grade, soic) v os 10 25 v ?40c < t a < +125c 65 v offset voltage drift (b grade, soic) v os / t ?40c < t a < +125c 0.1 0.2 5 v/c offset voltage (a grade) v os soic 15 50 v ?40c < t a < +125c 105 v msop 50 90 v ?40c < t a < +125c 220 v offset voltage drift (a grade) v os / t ?40c < t a < +125c soic 0.25 0.55 v/c msop 0.5 1.2 v/c input bias current i b ?1 ? 0.4 +1 na ?40c < t a < +125c ? 1.5 +1.5 na input offset current i os ? 0.5 + 0. 1 + 0.5 na ?40c < t a < +125c ? 1.0 +1. 0 na input voltage range ?3.8 +3 v common - mode rejection ratio cmrr v cm = ?3.8 v to +3v 122 140 db ?40c < t a < +125c 120 db large signal voltage gain a vo r l = 2 k , v o = ?3.0 v to +3.0 v 121 130 db ?40c < t a < +125c 120 db input capacitance c indm differential m ode 3 pf c incm common m ode 5 pf input resistance r in 100 m output characteristics output voltage high v oh i l = 1 ma +4.1 v ?40c < t a < +125c +4 v output voltage low v ol i l = 1 ma ? 3.5 v ?40c < t a < +125c ? 3.2 v output current i out v dropout < 1.6 v 10 ma short - circuit current i sc t a = 25 c 22 ma closed - loop output impedance z out f = 1 khz , a v = +1 0.05 power supply power supply rejection ratio psrr v s = 2.5 v to 18 v 123 128 db ?40c < t a < +125c 120 db supply current per amplifier i sy v o = 0 v 400 450 a ?40c < t a < +125c 65 0 a dynamic performance slew rate sr r l = 2 k 1 v/ s settling time to 0.1% t s v in =1 v step , r l = 4 k , a v = ? 1 2 s gain bandwidth product gbp a v = +1 4.0 mhz noise performance voltage noise e n p - p 0.1 hz to 10 hz 0.25 v p - p voltage noise density e n f = 1 hz 13 nv/hz f = 100 hz 7 nv/hz current noise density i n f = 1 khz 3 pa/hz multiple amplifiers channel separation c s f = 1 khz ?120 db
ada4077 - 2 data sheet rev. 0 | page 4 of 20 electrical character istics , 1 5.0 v v s y = 15 v, v cm = 0 v, t a = 25c, unless otherwise noted. table 3. parameter symbol test conditions/comments min typ max unit input characteristics offset voltage (b grade, soic) v os 10 35 v ?40c < t a < +125c 65 v offset voltage drift (b grade, soic) v os / t ?40c < t a < +125c 0.1 0.25 v/c offset voltage (a grade) v os soic 15 50 v ?40c < t a < +125c 105 v msop 50 90 v ?40c < t a < +125c 220 v offset voltage drift (a grade) v os / t ?40c < t a < +125c soic 0.2 0.55 v/c msop 0.5 1.2 v/c input bias current i b ? 1 ? 0.4 +1 na ?40c < t a < +125c ? 1.5 +1.5 na input offset current i os ?0.5 + 0.1 +0.5 na ?40c < t a < +125c ? 1.0 +1. 0 na input voltage range ? 13.8 +13 v common - mode rejection ratio cmrr v cm = ?13.8 v to +13 v 132 150 db ?40c < t a < +125c 130 db large signal voltage gain a vo r l = 2 k , v o = ?13.0 v to +13.0 v 125 130 db ?40c < t a < +125c 120 db input capacitance c indm differential m ode 3 pf c incm common m ode 5 pf input resistance r in 100 m output characteristics output voltage high v oh i l = 1 ma +14.1 v ?40c < t a < +125c +14 v output voltage low v ol i l = 1 ma ?13.5 v ?40c < t a < +125c ? 13.2 v output current i out v dropout < 1.2 v 10 ma short - circuit current i sc t a = 25 c 22 ma closed - loop output impedance z out f = 1 khz , a v = +1 0.05 power supply power supply rejection ratio psrr v s = 2.5 v to 18 v 12 3 128 db ?40c < t a < +125c 120 db supply current per amplifier i sy v o = 0 v 400 500 a ?40c < t a < +125c 650 a dynamic performance slew rate sr r l = 2 k 1 v/ s settling time to 0.01% t s v in = 10 v p - p, r l = 4 k , a v = ? 1 9 s settling time to 0.1% t s v in = 10 v p - p, r l = 4 k , a v = ? 1 8 s gain bandwidth product gbp a v = +1 3.9 mhz noise performance voltage noise e n p -p 0.1 hz to 10 hz 0.25 v p -p voltage noise density e n f = 1 hz 13 nv/hz f = 1 00 hz 7 nv/hz current noise density i n f = 1 khz 3 pa/hz multiple amplifiers channel separation c s f = 1 khz ?120 db
data sheet ada4077 - 2 rev. 0 | page 5 of 20 absolute maximum rat ings table 4. parameter rating supply voltage 36 v input voltage v sy differential input voltage v sy storage temperature range msop and soic_n packages ?65c to +150c operating temperature range ?40c to +125c junction temperature range r and rm packages ?65c to +150c lead temperature, soldering (10 sec) 300c thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc unit 8 - lead msop 190 44 c/w 8- lead soic_ n 158 43 c/w s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
ada4077 - 2 data sheet rev. 0 | page 6 of 20 pin configurations a nd function descript ions figure 4 . pin configuration, 8 - lead msop (rm suffix) figure 5 . pin configuration, 8 - lead soic_n (r suffix) table 6. ada4077 -2 pin function descriptions , msop and soic pin no. mnemonic description 1 out a output, channel a. 2 ?in a inverting input, channel a. 3 +in a noninverting input, channel a. 4 v? negative supply voltage. 5 +in b noninverting input, channel b. 6 ?in b inverting input, channel b. 7 out b output, channel b. 8 v+ positive supply voltage. out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t o p view (not to scale) 10238-004 out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4077-2 t o p view (not to scale) 10238-005
data sheet ada4077 - 2 rev. 0 | page 7 of 20 typical performance characteristics figure 6 . o ffset voltage distribution figure 7 . offset voltage distribution figure 8 . offset voltage vs. temperature figure 9 . offset voltage distribution figure 10 . offset voltage distribution figure 11 . offset voltage vs. temperature 0 20 40 v os (v) 60 80 100 120 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 10238-006 v sy = 5v mso p v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-144 v sy = 5v soic ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?50 0 50 temper a ture (c) ?25 25 75 100 125 v os (v) 10238-007 v sy = 5v 0 20 40 60 80 100 120 140 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 45 50 more v os (v) number of amplifiers 10238-003 v sy = 15v msop v os (v) ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 number of amplifiers 10 15 20 25 30 35 40 45 50 more 0 20 40 60 80 100 120 140 160 180 200 10238-009 v sy = 15v soic 0 2 4 6 8 10 12 14 16 ?50 0 50 temper a ture (c) ?25 25 75 100 125 v os (v) 10238-010 v sy = 15v
ada4077 - 2 data sheet rev. 0 | page 8 of 20 figure 12 . tcv os , msop figure 13 . v os vs. supplies figure 14 . v os v s. v cm figure 15 . tcv os , soic figure 16 . i sy vs. v sy figure 17 . input bias current v s. v cm 0 2 4 6 8 10 tcv os (nv/c) 12 14 16 18 ?0.75 ?0.70 ?0.65 ?0.60 ?0.55 ?0.50 ?0.45 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 number of amplifiers 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 10238-130 v sy = 15v msop 10 ?10 0 35 v os (v) v sy (v) 10238-134 ?5 0 5 5 10 15 20 25 30 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 ?20 ?15 ?10 ?5 0 20 15 10 5 v os (v) v cm (v) 10238-112 a verage C3 a verage a verage +3 v sy = 15v 0 10 20 30 40 50 60 70 80 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 more tcv os (v/c) number of amplifiers 10238-008 v sy = 15v soic 0.9 ?0.1 0 35 supply current (ma) supply voltage (v) 10238-126 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5 10 15 20 25 30 800 0 ?20 ?15 ?10 ?5 0 20 15 10 5 i b (pa) v cm (v) 10238-115 average C3 average average +3 100 200 300 400 500 600 700 v sy = 15v
data sheet ada4077 - 2 rev. 0 | page 9 of 20 figure 18 . input bias current figure 19 . input bias current vs. temper a ture figure 20 . v ol vs. load figure 21 . input bias current figure 22 . input bias current vs. temperature figure 23 . v ol vs. load 350 0 number of amplifiers input bias current (na) 10238-013 50 100 150 200 250 300 ?1.0 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 more v sy = 5v ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 i b (na) ?0.2 ?0.1 0 ?50 0 50 100 ?25 temper a ture (c) 25 75 125 + i b ? i b 10238-014 v sy = 5v 1800 1200 0.001 10 v ol ? v ss (mv) load current (ma) 10238-118 1400 1600 0.01 0.1 1 v sy = 5v 400 0 number of amplifiers input bias current (na) 10238-016 50 100 150 200 250 300 350 ?1 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 more v sy = 15v ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 i b (na) ?0.2 ?0.1 0 ?50 0 50 100 ?25 temper a ture (c) 25 75 125 + i b ? i b 10238-017 v sy = 15v 1800 1200 0.001 10 v ol ? v ss (mv) load current (ma) 10238-122 1400 1600 0.01 0.1 1 v sy = 15v
ada4077 - 2 data sheet rev. 0 | page 10 of 20 figure 24 . o utput drop out v oltage vs. load figure 25 . open - loop gain and phase vs. frequency figure 26 . output voltage swing vs. temperature figure 27 . o utput drop out v oltage vs. load figure 28 . open - loop gain and phase vs. frequency figure 29 . output voltage swing vs. temperature 1200 600 0.001 10 load current (ma) 10238-119 800 1000 0.01 0.1 1 v dd ? v oh (mv) v sy = 5v 120 90 60 30 0 ?30 135 90 45 0 ?45 ?90 10k 10m 1m 100k open-loop gain (db) phase margin (degrees) frequency (hz) v sy = 5v r l = 2k c l = 100pf phase gain 10238-022 ?6 ?4 ?2 0 2 4 6 ?50 0 50 100 ?25 25 temper a ture (c) output vo lt age swing (v) 75 125 v oh v o l 10238-021 v sy = 5v 1200 600 0.001 10 v dd ? v oh (mv) load current (ma) 10238-121 800 1000 0.01 0.1 1 v sy = 15v 120 90 60 30 0 ?30 135 90 45 0 ?45 ?90 10k 10m 1m 100k open-loop gain (db) phase margin (degrees) frequency (hz) v sy = 15v r l = 2k? c l = 100pf phase gain 10238-027 ?50 0 50 1 ?25 25 temper a ture (c) output vo lt age swing (v) 75 125 v oh v o l 13.2 13.4 13.6 13.8 14.0 14.2 14.4 10238-140 v sy = 15v
data sheet ada4077 - 2 rev. 0 | page 11 of 20 figure 30 . ps rr vs. frequency , 5 v figure 31 . cmrr vs. temperature figure 32 . cm rr vs. frequency figure 33 . psrr vs. frequency, 1 5 v figure 34 . cmrr vs. temperature figure 35 . psrr vs. temperature ?20 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) psrr? psrr+ v sy = 5v 10238-034 141 142 143 144 145 146 147 148 149 150 151 152 ?50 0 50 ?25 25 temper a ture (c) cmrr (db) 75 100 125 10238-030 v sy = 5v cmrr (db) 0 20 40 60 80 100 120 140 100 1k 10k 100k 1m 10m frequenc y (hz) v sy = 15v v sy = 5v 10238-029 ?20 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) psrr? psrr+ v sy = 15v 10238-037 153 154 155 156 157 158 159 ?50 0 50 ?25 25 temper a ture (c) cmrr (db) 75 100 125 10238-033 v sy = 15v 124 125 126 127 128 129 130 131 132 133 ?50 0 50 100 ?25 25 psrr (db) temper a ture (c) 75 125 10238-035 v sy = 5v t o 15v
ada4077 - 2 data sheet rev. 0 | page 12 of 20 figure 36 . closed - loop gain vs. frequency figure 37 . output impedance vs. frequency figure 38 . large signal transient response figure 39 . closed - loop gain vs. frequency figure 40 . output impedance vs. frequency figure 41 . large signal transient response 50 ?50 1k 10k 100k 100m 10m 1m clsoed-loop gain (db) frequency (hz) ?40 ?30 ?20 ?10 0 10 20 30 40 g = 1 g = 10 g = 100 10238-028 v sy = 5v 0.001 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out (?) frequenc y (hz) a v = 100 v sy = 5v a v = 10 a v = 1 10238-036 time (100s/div) 0v volt age (0.2v/div) v sy = 5v v in = 1v p-p a v = 1 r l = 2k? c l = 300pf 10238-040 50 ?50 1k 10k 100k 100m 10m 1m clsoed-loop gain (db) frequency (hz) ?40 ?30 ?20 ?10 0 10 20 30 40 g = 1 g = 10 g = 100 10238-031 v sy = 15v 0.001 0.01 0.1 1 10 100 1k 100 1k 10k 100k 1m 10m z out (?) frequenc y (hz) a v = 100 v sy = 15v a v = 10 a v = 1 10238-039 time (100s/div) vo lt age (1v/div) v sy = 15v v in = 4v p-p a v = 1 r l = 2k? c l = 300pf 10238-043 0v
data sheet ada4077 - 2 rev. 0 | page 13 of 20 figure 42 . small signal transient response figure 43 . positive overload recovery figure 44 . negative overload recovery figure 45 . small signal transient response figure 46 . positive overload recovery figure 47 . negative overload recovery time (100s/div) volt age (50mv/div) v sy = 5v v in = 200mv p-p a v = 1 r l = 2k? c l = 1000pf 10238-041 0v time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?1 1 3 5 output vo lt age (v) v sy = 5v a v = ?100 v in = 200mv r l = 10k? input output 10238-046 time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?5 ?3 ?1 1 output vo lt age (v) v sy = 5v a v = ?100 v in = 200mv r l = 10k? input output 10238-047 time (100s/div) vo lt age (50mv/div) v sy = 15v v in = 200mv p-p a v = 1 r l = 2k? c l = 1000pf 10238-044 0v time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?2 0 2 4 6 8 10 12 14 16 output vo lt age (v) v sy = 15v a v = ?100 v in = 200mv r l = 10k? 10238-146 input output time (10s/div) 0.5 0 ?0.5 input vo lt age (v) ?15 ?10 ?5 0 output vo lt age (v) v sy = 15v a v = ?100 v in = 200mv r l = 10k? input output 10238-051
ada4077 - 2 data sheet rev. 0 | page 14 of 20 figure 48 . small signal overshoot vs. load capacitance figure 49 . positive settling time figure 50 . voltage noise density vs. frequency figure 51 . small signal overshoot vs. load capacitance figure 52 . positive settling time figure 53 . voltage noise corner frequency 0 50 10 100 1k 10k overshoot (%) load ca p aci t ance (pf) os+ os? v sy = 5v v in = 200mv p-p a v = 1 r l = 2k? 5 10 15 20 25 30 35 40 45 10238-042 450 ?100 ?1 0 1 2 3 4 error band voltage (mv) input voltage (v) time (s) 10238-149 v sy = 5v v in = 1v p-p a v = ?1 input output 0 0.2 0.4 0.6 0.8 1 1.2 ?50 0 50 100 150 200 250 300 350 400 1k 100 10 1 10 10m 1m 100k 10k 1k 100 voltage noise density (nv/hz) frequency (hz) ch a ch b v sy = 15v a v = +1 10238-053 0 50 10 100 1k 10k overshoot (%) load ca p aci t ance (pf) os+ os? v sy = 15v v in = 200mv p-p a v = 1 r l = 2k? 5 10 15 20 25 30 35 40 45 10238-045 500 400 300 200 100 0 ?100 12 10 8 6 4 2 0 ?5 0 5 10 15 20 error band voltage (mv) input voltage (v) time (s) 10238-152 v sy = 15v v in = 10v p-p a v = ?1 input output 100 0 0 3.0 voltage noise corner (nv/hz) frequency (hz) 10238-153 10 20 30 40 50 60 70 80 90 0.5 1.0 1.5 2.0 2.5 v sy = 15v
data sheet ada4077 - 2 rev. 0 | page 15 of 20 figure 54 . thd + n vs. frequency figure 55 . 0.1 hz to 10 hz noise figure 56 . thd + n vs. frequency figure 57 . 0.1 hz to 10 hz noise figure 58 . channel separation 0.001 0.0001 10 10k 1k 100 100k thd + n (%) frequency (hz) 10238-155 v sy = 5v r l = 10k? v in = 1v rms a v = +1 time (1s/div) input vo lt age (50nv/div) v sy = 5v v cm = 0v 10238-054 0.001 0.0001 10 10k 1k 100 100k thd + n (%) frequency (hz) 10238-158 v sy = 15v r l = 10k? v in = 1v rms a v = +1 time (1s/div) input vo lt age (50nv/div) v sy = 15v v cm = 0v 10238-058 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 100 100k 10k 1k 1m channel separation (db) frequency (hz) 10238-244 v sy = 15v v in = 3.5v p-p a v = +1
ada4077 - 2 data sheet rev. 0 | page 16 of 20 theory of operation the ada4077 - 2 is the sixth generation of the analog devices, inc., industry - standa rd op07 amplifier family. the ada4077 - 2 is a high precision, low noise operational amplifier with a combination of extremely low offset voltage and very low input bias currents. unlike jfet amplifiers, the low bias and offset currents are relatively insensitive to ambient temperatures, even up to 125c. the analog devices proprietary process technology and linear design expertise have produced a high voltage amplifier with superior performance to the op07 , op77 , op177 , and op 1 177 in tiny , 8 - lead soic and 8 - lead msop package s . de spite its small size, the ada4077 - 2 offers numerous improvements, including low wideband noise, wide bandwidth, lower offset and offset drift, lower input bias current, and complete freedom from phase inversion. the ada4077 - 2 has a specified operating temperature range of ? 40 c to +125 c with a msl1 rat ing , which is as wid e as any similar device in a plastic surface - mount package. this is increasingly important as pcb and overall system sizes continue to shrink, causing internal system temperatures to rise. in the ada4077 - 2 , p ower consumption is reduced by a factor of four from the op177 , and bandwidth and slew rate have both increase d by a factor of six . the low power dissipation and very stable performance vs. temperature also act to reduce warm - up drift errors to insignificant levels. inputs are protected internally from overvoltage conditions referenced to either supply rail. like any high performance amplifier, maximum performance is achieved by following appropriate circuit and pcb guidelines .
data sheet ada4077 - 2 rev. 0 | page 17 of 20 application s information output phase reversa l phase reversal is defined as a change of polarity in the amplifier transfer function. many operational amplifiers exhibit phase reversal when the voltage applied to the input is greater than the maximum common - mode voltage. in some instances, this can caus e permanent damage to the amplifier. in feedback loops, it can result in system lockups or equipmen t damage. the ada4077 - 2 is immune to phase reversal problems even at input voltages beyond the supplies. fi gure 59 . no phase reversal low power linearized r td a common application for a single element varying bridge is an rtd ther mometer amplifier, as shown in figure 60 . the excitation is delivered to the bridge by a 2.5 v reference applied at the top of the bridge. rtds can have a thermal resistance as high as 0.5c to 0.8c per mw. to minimize errors due to resistor drift, the current through each leg of the bridge must be kept low. in this circuit, the amplifier supply current flows through the bridge. however, at the ada4077 - 2 maximum supply current of 500 a, the rtd dissipates less than 0.1 mw of p ower, even at the highest resis tance. errors due to power dissipation in the bridge are kept under 0.1c. calibration of the bridge is made at the minimum value of the temperature to be measured by adjusting rp until the output is zero. to calibrate the output span, set the full - scale and linearity potentiometers to midpoint and apply a 500c temperature to the sensor or substitute the equivalent 500c rtd resistance. adjust the full - scale potentiometer for a 5 v output. finally, apply 250c or the equivalent rtd resistance and adjust the linearity potentiometer for 2.5 v output. the circuit achieves better than 0.5c accuracy after adjustment. figure 60 . low power linearized rtd cir cuit 2 ch1 5.00v ch2 5.00v m10.0ms a ch1 300mv 1 t 0.000% 10238-063 200? 500? 4.37k? 100? 100? 20? 4.12k? 4.12k? 5k? 49.9k? adr4525 +15v 0.1f v+ 100? rtd 1/2 ada4077-2 7 6 5 1/2 ada4077-2 1 8 2 3 4 v? v out v out 10238-064
ada4077 - 2 data sheet rev. 0 | page 18 of 20 proper board layout the ada4077 - 2 is a high precision device. to ensure optimum performance at the pcb level, care must be taken in the design of the board layout. to avoid leakage currents, maintain a clean and moisture - free board surface. coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. keeping supply traces short and properly bypassing the power supplies minimizes power sup ply disturbances caused by output current variation, such as when driving an ac signal into a heavy load. connect b ypass capacitors as closely as possible to the device supply pins. stray capacitances are a concern at the outputs and the inputs of the ampl ifier. it is recommended that signal traces be kept at least 5 mm from supply lines to minimize coupling. a variation in temperature across the pcb can cause a mismatch in the seebeck voltages at solder join ts and other points where dissi milar metals are in contact, resulting in thermal voltage errors. to minimize these thermocouple effects, orient resistors so heat sources warm both ends equally. input signal paths should contain matching numbers and types of components, where possible , to match the numbe r and type of thermocouple junctions. for example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. place m atching components in close proximity to each other and orient them in the same manner. ensure that leads are of equal length so that thermal conduction is in equilibrium. keep heat sources on the pcb as far away from amplifier input circuitry as is practical. the use of a ground plane is highly recommended. a ground plane reduces emi noise and helps to maintain a constant temperature across the circuit board.
data sheet ada4077 - 2 rev. 0 | page 19 of 20 packaging and ordering information outline dimensions figure 61 . 8 - lead mini small outline package [msop] (rm - 8) dimensions shown in millimeters figure 62 . 8 - lead standard small outline package [soic_n] narrow body (r - 8) dimensions shown in millimeters and (inches) c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - a a 6 0 0 . 8 0 0 . 5 5 0 . 4 0 4 8 1 5 0 . 6 5 b s c 0 . 4 0 0 . 2 5 1 . 1 0 m a x 3 . 2 0 3 . 0 0 2 . 8 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 0 9 3 . 2 0 3 . 0 0 2 . 8 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 1 0 - 0 7 - 2 0 0 9 - b c ontrolling dimensions are in millimeters; inch dimensions (in p arentheses) are rounded-off millimeter equiv alents for reference onl y and are not appropria te for use in design. compliant t o jedec st andards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) sea ting plane 0.25 (0.0098) 0.10 (0.0040) 4 1 8 5 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10
ada4077 - 2 data sheet rev. 0 | page 20 of 20 ordering guide model 1 temperature range package description package option branding ada4077 -2- armz ?40c to +125c 8- lead mini small outline package [msop] rm -8 a2x ada4077 - 2 armz - r7 ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2x ada4077 -2 armz -rl ?40c to +125c 8- lead mini small outline package [msop] rm -8 a2x ada4077 - 2ar z ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4077 - 2ar z-r7 ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4077 - 2ar z-rl ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4077 - 2br z ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4077 - 2br z-r7 ?40c to +125c 8- lead standard small outline package [soic_n] r -8 ada4077 - 2br z-rl ?40c to +125c 8- lead standard small outline package [soic_n] r -8 1 z = rohs compliant part. ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10238 - 0 - 10/12(0) www.analog.com/ ada4077 - 2

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